A typical flip-chip LED has reflective p and n contacts on a bottom surface of the LED, and the contacts are directly connected to bonding pads on a submount. Light generated by the LED is primarily emitted through the top surface of the LED surface. In this way, there are no top contacts that block the light, and wire bonds are not needed.
During fabrication, a submount wafer is populated with an array of LED dies, and the LED dies are further processed as a batch on the wafer. Ultimately, the wafer is singulated by, for example, sawing.
The efficiency of flip-chip gallium-nitride (GaN) LEDs can be increased by removing the transparent sapphire growth substrate after all the LED layers have been epitaxially grown. After the removal of the substrate, the exposed GaN layer is etched to thin the layer and to create a roughened surface to increase light extraction. A good etching technique for the exposed layer is photo-electrochemical (PEC) etching, which involves electrically biasing the layer to be etched, immersing the LED in a base solution (e.g., KOH) containing a biased electrode, and applying UV light to the exposed layer. Exposure to the UV light generates electron-hole pairs in the semiconductor layer. The holes migrate to the surface of the GaN layer under the influence of the electric field, then react with the GaN and base solution at the surface to break the GaN bonds. The exposed layer is typically an N-type confining layer or a semi-insulating layer (e.g., a buffer layer) over the N-type layer.
One possible method for biasing the exposed N-type LED layer is to provide a grounded metal pattern on the submount wafer that connects to all the N-metal bonding pads on the wafer so the exposed N-type layer is electrically biased during the PEC etching. After the PEC etching, when the submount wafer is sawed to dice the LEDs, the biasing metal pattern is cut so has no effect on the subsequent operation of each singulated LED.
Applicant has found that one problem with using the interconnecting metal on the submount for biasing is that, after sawing the submount wafer for dicing, the traces connecting to the N-metals are exposed on the sidewalls. This reduces the creepage distance between the active N electrodes and the grounding pads on the backside. This limits the maximum number of LEDs that can be connected in series before creepage can develop between the N-metal and ground.
Further, the sawed metal can be smeared along the sidewall of the submount die during the sawing and form a leakage path across the submount edge or side or to another lead. Another problem with the interconnecting metal is that an LED string cannot be tested unless the metal is cut prior to the singulation sawing. This adds a process step. Further, when forming multiple mini-LEDs in a single die, the N-layers cannot be interconnected with a sawable interconnection metal.
What is needed is an efficient technique to bias the exposed layer of LEDs mounted on a submount wafer during PEC etching that does not have the drawbacks of the metal interconnect described above.